`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/06/24 14:37:44
// Design Name: 
// Module Name: bin_to_bcd_8bit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module bin_to_bcd_8bit(
    input [7:0] binary_in,
    output [11:0] bcd_out
);


    wire [19:0] pipe1_reg, pipe2_reg, pipe3_reg, pipe4_reg;
    wire [19:0] pipe5_reg, pipe6_reg, pipe7_reg, pipe8_reg;


    assign pipe1_reg = {12'h000, binary_in} << 1;


    wire [3:0] p1_h = (pipe1_reg[19:16] >= 5) ? pipe1_reg[19:16] + 3 : pipe1_reg[19:16];
    wire [3:0] p1_t = (pipe1_reg[15:12] >= 5) ? pipe1_reg[15:12] + 3 : pipe1_reg[15:12];
    wire [3:0] p1_o = (pipe1_reg[11:8]  >= 5) ? pipe1_reg[11:8]  + 3 : pipe1_reg[11:8];
    assign pipe2_reg = {p1_h, p1_t, p1_o, pipe1_reg[7:0]} << 1;


    wire [3:0] p2_h = (pipe2_reg[19:16] >= 5) ? pipe2_reg[19:16] + 3 : pipe2_reg[19:16];
    wire [3:0] p2_t = (pipe2_reg[15:12] >= 5) ? pipe2_reg[15:12] + 3 : pipe2_reg[15:12];
    wire [3:0] p2_o = (pipe2_reg[11:8]  >= 5) ? pipe2_reg[11:8]  + 3 : pipe2_reg[11:8];
    assign pipe3_reg = {p2_h, p2_t, p2_o, pipe2_reg[7:0]} << 1;


    wire [3:0] p3_h = (pipe3_reg[19:16] >= 5) ? pipe3_reg[19:16] + 3 : pipe3_reg[19:16];
    wire [3:0] p3_t = (pipe3_reg[15:12] >= 5) ? pipe3_reg[15:12] + 3 : pipe3_reg[15:12];
    wire [3:0] p3_o = (pipe3_reg[11:8]  >= 5) ? pipe3_reg[11:8]  + 3 : pipe3_reg[11:8];
    assign pipe4_reg = {p3_h, p3_t, p3_o, pipe3_reg[7:0]} << 1;


    wire [3:0] p4_h = (pipe4_reg[19:16] >= 5) ? pipe4_reg[19:16] + 3 : pipe4_reg[19:16];
    wire [3:0] p4_t = (pipe4_reg[15:12] >= 5) ? pipe4_reg[15:12] + 3 : pipe4_reg[15:12];
    wire [3:0] p4_o = (pipe4_reg[11:8]  >= 5) ? pipe4_reg[11:8]  + 3 : pipe4_reg[11:8];
    assign pipe5_reg = {p4_h, p4_t, p4_o, pipe4_reg[7:0]} << 1;


    wire [3:0] p5_h = (pipe5_reg[19:16] >= 5) ? pipe5_reg[19:16] + 3 : pipe5_reg[19:16];
    wire [3:0] p5_t = (pipe5_reg[15:12] >= 5) ? pipe5_reg[15:12] + 3 : pipe5_reg[15:12];
    wire [3:0] p5_o = (pipe5_reg[11:8]  >= 5) ? pipe5_reg[11:8]  + 3 : pipe5_reg[11:8];
    assign pipe6_reg = {p5_h, p5_t, p5_o, pipe5_reg[7:0]} << 1;


    wire [3:0] p6_h = (pipe6_reg[19:16] >= 5) ? pipe6_reg[19:16] + 3 : pipe6_reg[19:16];
    wire [3:0] p6_t = (pipe6_reg[15:12] >= 5) ? pipe6_reg[15:12] + 3 : pipe6_reg[15:12];
    wire [3:0] p6_o = (pipe6_reg[11:8]  >= 5) ? pipe6_reg[11:8]  + 3 : pipe6_reg[11:8];
    assign pipe7_reg = {p6_h, p6_t, p6_o, pipe6_reg[7:0]} << 1;


    wire [3:0] p7_h = (pipe7_reg[19:16] >= 5) ? pipe7_reg[19:16] + 3 : pipe7_reg[19:16];
    wire [3:0] p7_t = (pipe7_reg[15:12] >= 5) ? pipe7_reg[15:12] + 3 : pipe7_reg[15:12];
    wire [3:0] p7_o = (pipe7_reg[11:8]  >= 5) ? pipe7_reg[11:8]  + 3 : pipe7_reg[11:8];
    assign pipe8_reg = {p7_h, p7_t, p7_o, pipe7_reg[7:0]} << 1;


    assign bcd_out = pipe8_reg[19:8];

endmodule
